A common method of generating a high frequency system clock from a low frequency reference clock is through the use of a phase locked loop circuit. There are various methods of implementing a phase locked loop circuit, but all phase locked loop circuits have three essential portions: a phase detector portion, a loop filter portion, and a voltage controlled oscillator portion. The phase detector portion has a first input for receiving a reference clock signal, and a second input for receiving the output of the voltage controlled oscillator portion. The output of the voltage controlled oscillator portion is also the output of the phase locked loop circuit. The phase detector portion has an output that is connected to an input of the loop filter portion, and the loop filter portion has an output that is connected to an input of the voltage controlled oscillator portion.
In operation, the output of the phase detector portion provides a signal which is proportional to any phase difference between the two signals at the two inputs mentioned above. In response to the phase detector portion, the loop filter portion provides an output signal that is a function of the input signal from the phase detector portion. The voltage controlled oscillator portion provides an output frequency that is proportional to the output of the loop filter portion. As mentioned above, the output signal of the voltage controlled oscillator portion is connected back to the second input of the phase detector portion as feedback information. The feedback information is necessary in order for the output signal of the voltage controlled oscillator portion to phase lock with the reference clock signal.
Depending on the application, each of the portions of the phase locked loop circuit is intentionally implemented by using specific digital or analog circuits. For example, a phase locked loop circuit that is implemented using a digital phase detector, a digital loop filter and a digitally controlled oscillator has an advantage of improved operating stability with respect to temperature and supply voltage variations as compared to an analog implementation. However, a digitally controlled oscillator has a potential disadvantage in that an additional clocking signal that is higher in frequency than the phase locked loop circuit frequency is required to control only the digitally controlled oscillator.
Another common phase locked loop implementation utilizes a digital phase detector, an analog loop filter, and an analog voltage controlled oscillator. An advantage to this implementation is that the analog voltage controlled oscillator does not require a separate higher frequency clock. A possible disadvantage is that the analog loop filter implementation requires capacitive and resistive components external to the phase locked loop circuit that add cost and reduce reliability.
In general, by implementing the various components using digital circuitry, as opposed to analog circuitry, a more stable circuit design is achieved. In contrast, an analog implementation of a phase locked loop circuit has the advantages of avoiding quantization errors associated with conversion to digital quantities and avoiding frequency aliasing errors associated with digital design techniques. Also, in a completely analog phase locked loop circuit, a higher operating frequency may be obtained for a crystal of predetermined frequency as compared with a completely digital phase locked loop circuit.
Phase locked loop circuits are implemented using a proportional-integral control term method. Each control term provides a specific effect on the performance of the phase locked loop circuit. The proportional term determines, in part, a dampening factor of the phase locked loop circuit. The integral term compensates for a frequency offset error in the phase locked loop circuit.
Phase locked loop circuits are commonly utilized in a high performance telecommunication transceiver within a telecommunication system, where a transceiver is a telecommunication device that can both transmit and receive data bit information. A primary reason why a phase locked loop circuit is used within a high performance telecommunication transceiver is to provide data-clock synchronization between a transmitter and a receiver. Failure to establish data-clock synchronization can cause "cycle slip". When cycle-slip occurs, some data bits being transmitted are not received by another transceiver within the telecommunication system, and the data bits that are not received as a result of cycle-slip are said to have been dropped or ignored.
A common problem associated with phase locked loop circuits is an intrinsic frequency jitter at the output, where frequency jitter is a deleterious variation in the output frequency. Not all applications of phase locked loop circuits are sensitive to frequency jitter; however, frequency jitter is a primary concern in telecommunications.
In telecommunication systems that utilize high performance transceivers, data signal processing techniques are utilized. These data signal processing techniques require that the magnitude of the frequency jitter be at a minimum. For example, the frequency jitter tolerance of such a high performance telecommunication system, like a U-transceiver, is specified by an international standards committee, ANSI, and is illustrated in FIG. 1. The graph of FIG. 1 illustrates the magnitude of the output frequency jitter as measured in pico-seconds, on the vertical axis, as a function of frequency, on the horizontal axis. The graph demonstrates that as frequency increases, the magnitude of the allowed frequency jitter also increases, and as frequency decreases, the magnitude of the allowed frequency jitter decreases.
A first order phase locked loop circuit has a loop filter portion with only a proportional control term. Therefore, wider noise bandwidth exists in the phase locked loop circuit, and any noise or jitter in the input reference signal is not filtered. A known method of reducing the frequency jitter at the output of a first order phase locked loop circuit is to control the output frequency via a number of ratioed switchable capacitors at the output of a crystal oscillator circuit. The switched capacitors are controlled directly by the output of a phase detector. In such a circuit, magnitude of the frequency jitter can be forcibly or `hard` limited to a predetermined value by limiting the maximum frequency that the oscillator can produce to the predetermined value. A disadvantage to conventional first order phase locked loop circuits using ratioed switched capacitors at the output is that the frequency offset compensation of the phase locked loop is limited.